Fault detection in electrical circuits is an important factor in quality control of the manufacturing processes by which circuits of ever decreasing size and increasing complexity are manufactured in ever increasing quantities. For a general description of fault testing, including one particular approach thereto, reference may be made, for example, to U.S. Pat. No. 4,074,851--Eichelberger et al. This patent is of further interest, with respect to the present invention, for its disclosure of means for conversion from sequential circuit to combinational circuit logic to facilitate testing. The present invention is directed to apparatus and a method for testing a combinational circuit, but would find further application in the testing of a sequential circuit including such logic conversion means. U.S. Pat. No. 4,039,813--Kregness is also of interest for its disclosure of an apparatus and method for diagnosing a digital circuit wherein a test step counter is utilized in conjunction with a register, memory, and error comparator, which translates detected errors into a displayable code for maintenance isolation.
Of more specific interest with respect to the present invention is certain literature references dealing with specific input-output analyses as fault detection techniques. In this regard, reference may be made to Bennetts and Hurst, RADEMACHER-WALSH SPECTRAL TECHNIQUES, A NEW TOOL FOR DIGITAL NETWORK FAULT DIAGNOSIS?, Digest of Papers, Seventh Annual International Conference on Fault Tolerant Computing, IEEE Catalog No. 77CH1223-7C (1977).
Also of interest are Savir, SYNDROME-TESTABLE DESIGN OF COMBINATIONAL CIRCUITS, Digest of Papers, The Ninth Annual International Symposium on Fault Tolerant Computing, IEEE Publication No. 79CH1396-1C, Tzidon et al, A PRACTICAL APPROACH TO FAULT DETECTION IN COMBINATIONAL NETWORKS, IEEE Transactions on Computers, Volume C-27, No. 10, October, 1978, pages 968-971.
The test approach as set forth in these papers is limited as to the kinds of faults that can be detected and is therefore more restrictive in application than the present invention.
Accordingly, notwithstanding these prior art teachings, there remains a need for simplified test methods and apparatus capable of quickly detecting faults, particularly stuck-at pin faults in an electrical circuit, and particularly a need for such a test method and apparatus which is sufficiently simple to facilitate incorporation of the test circuit in the circuit to be tested.